Complementary mask, fabrication method thereof, exposure method, semiconductor device, and fabrication method thereof

ABSTRACT

A complementary mask has a plurality of pattern forming regions  34   a,    34  having arranged on them complementary patterns  26, 28  obtained by dividing first circuit patterns into complementary patterns  26, 28  complementary with each other and formed by openings. The complementary patterns  26, 28  are arranged in the pattern forming regions  34   a,    34   b  so that pattern densities of the pattern forming regions  34   a,    34   b  become substantially the same.

TECHNICAL FIELD

[0001] The present invention relates to complementary masks used in forexample an exposure process in the process of manufacture of asemiconductor device and a method of fabrication of the same, anexposure method, and a semiconductor device and a method of productionof the same.

BACKGROUND ART

[0002] In a charged particle beam exposure apparatus, for example, anelectron beam exposure apparatus, when preparing circuit patterns(element formation patterns) of a large scale integrated circuit etc., ahigh level of processing capability per unit time (throughput) isrequired.

[0003] An electron beam exposure apparatus answering such a demand isdisclosed in for example Japanese Unexamined Patent Publication (Kokai)No. 5-160012 and Japanese Patent No. 2951947.

[0004]FIG. 1 is a schematic view of an example of an electron beamexposure apparatus of a type similar to that disclosed in the abovepublications. This electron beam exposure apparatus 10 is configured asa so-called LEEPL type designed to make a wafer or other specimen(exposed body) moved at suitable times by operation of a table in astate with a stencil mask 20 fixed. In the description of the presentapplication, “stencil mask” refers to a mask having opening areas withno substances present in the spaces.

[0005] As shown in FIG. 1, the electron beam exposure apparatus 10 isprovided with an electron beam source 12 for emitting an electron beamEb, a focusing optical system 14 for focusing the electron beam Eb, amain deflector 16 for deflecting the electron beam Eb focused by thefocusing optical system 14, and a fine adjustment deflector 18 andprojects the electron beam Eb passed through the fine adjustmentdeflector 18 via the stencil mask 20 to the surface of the specimen 21.

[0006] The electron beam exposure apparatus 10 is provided with a maskstage for holding the stencil mask 20 and the table for holding aspecimen 21 at a location where the circuit patterns (opening patterns)are projected by the electron beam Eb passed through the stencil mask20.

[0007] In the electron beam exposure apparatus 10 having the aboveconfiguration, the exposure is started in a state where the stencil mask20 is mounted on the mask stage and then a specimen 21 having a resistfilm (not illustrated) coated on the surface is placed on the table.

[0008] At this time, when the electron beam Eb is emitted from theelectron beam source 12, the electron beam Eb passed through thefocusing optical system 14, main deflector 16, and fine adjustmentdeflector 18 passes through the circuit patterns of the stencil mask 20,then is exposed by projection onto the resist film at the surface of thespecimen 21 as the circuit patterns.

[0009] In the electron beam exposure apparatus 10, however, the electronbeam Eb used for the projection of the circuit patterns has a naturewhereby energy is absorbed even when passing through a transparentsubstance for visible light or ultraviolet ray, so the stencil mask 20cannot be configured by transparent, strong silica glass or the like.For this reason, in order to make the electron beam Eb pass well at thetime of projection exposure, there is no method other than the method offorming the circuit patterns by openings.

[0010] In this way, the stencil mask 20 is a self-supporting typetransmission mask where circuit patterns of regions passing the electronbeam are all formed by openings, therefore cannot be provided withdonut-shaped patterns where peripheries are all surrounded by openings.Accordingly, it is impossible to expose by projection donut-shapedpatterns onto a specimen 21 by merely using one such stencil mask 20.

[0011] In order to solve the problem of the above donut-shaped patterns,the complementary mask division method for dividing one circuit patternamong a plurality of complementary stencil masks is disclosed in forexample Japanese Examined Patent Publication (Kokoku) No. 7-66182.

[0012] In the complementary mask division method disclosed in thispublication, the relatively simple layout of a semiconductor chip isdivided into a plurality of sections, and the divided sections areassigned to two complementary stencil masks. Further, these twocomplementary stencil masks are used to sequentially expose sections ofthe layout formed at the complementary stencil masks onto the surface ofthe specimen (exposed body) and thereby transfer the entire circuitpatterns.

[0013] In the description of the present application, “complementarymasks” mean masks dividing patterns of a certain section and placing theparts on a plurality of masks or placing them on different areas of thesame mask and able to form the patterns of that section as beforedivision by overlaying the masks or different areas of the same mask tooverlay the divided parts of the patterns.

[0014] Also, in the description of the present application,“complementary stencil masks” mean stencil masks dividing patterns of acertain section and placing the parts on a plurality of stencil masks orplacing them on different areas of the same stencil mask and able toform the patterns of that section as before division by overlaying thestencil masks or different areas of the same stencil mask to overlay thedivided parts of the patterns.

[0015] In the field of production of semiconductor integrated circuitsin recent years, in response to the demand for further largerintegration, there has been a trend toward an increase of the number ofdevices configuring the semiconductor integrated circuits and greaterminiaturization of each device. Due to this, the circuit patternscomprised by the openings for exposing by projection the patterns of thedevices onto the specimen by an irradiated electron beam are becomingmore miniaturized.

[0016] Accordingly, the pattern density of the openings forming circuitpatterns has increased. With the complementary stencil masks used in theabove conventional complementary mask division method or the like, themechanical strength falls, distortion or other deformation becomes easyto occur in the circuit patterns, and even breakage occurs in remarkablecases.

[0017] When distortion or other deformation occurs in complementarystencil masks, overlay accuracy no longer can be carried out between thespecimen and the complementary stencil masks. Also, the electron beampassed through the distorted circuit patterns is exposed by projectiononto the specimen, so the accurate circuit patterns cannot betransferred.

DISCLOSURE OF THE INVENTION

[0018] The present invention was made in consideration with abovecircumstances and has as an object thereof to provide complementarymasks improved in mechanical strength, not causing distortion in thecircuit patterns, accurately aligned with the specimen, and able toaccurately transfer the circuit patterns onto the specimen and a methodof fabrication of the same.

[0019] Further, another object of the present invention is to provide anexposure method using such complementary masks and a semiconductordevice and a method of production of the same.

[0020] To attain the above objects, a complementary mask of the presentinvention is a mask which has a plurality of pattern forming regionshaving arranged on it complementary patterns obtained by dividing firstcircuit patterns into complementary patterns complementary with eachother and formed by openings and which have the complementary patternsarranged in the pattern forming regions so that pattern densities of thepattern forming regions become substantially the same.

[0021] To attain the above objects, a method of fabrication of acomplementary mask of the present invention has a step of dividing firstcircuit patterns into a plurality of pattern forming regions so thatpattern densities become substantially the same and assigningcomplementary patterns complementary with each other to the patternforming regions and a step of forming holes comprised by complementarypatterns of the pattern forming regions so that the pattern formingregions are adjacent on the same mask substrate.

[0022] To attain the above objects, an exposure method of the presentinvention has a step of using a first complementary mask, which isprovided adjacent to each other with a plurality of pattern formingregions on which are arranged complementary patterns obtained bydividing first circuit patterns into complementary patternscomplementary with each other and formed by openings and which has thecomplementary patterns arranged in the pattern forming regions so thatthe pattern densities of the pattern forming regions becomesubstantially the same, to make a charged particle beam scan all of thepattern forming regions of the first complementary mask and transfer thecomplementary patterns to an exposed body, and a shifting andtransferring step of shifting the mask by exactly one pattern formingregion worth of distance and making the charged particle beam scan allof the pattern forming regions of the first complementary mask again totransfer the complementary patterns to the exposed body, and repeats theshifting and transferring step to transfer the complementary patterns ofall the pattern forming regions and thereby transfer the first circuitpatterns to the exposed body.

[0023] To attain the above objects, a semiconductor device of thepresent invention is one obtained by a method which has a step of usinga complementary mask, which is provided adjacent to each other with aplurality of pattern forming regions on which are arranged complementarypatterns obtained by dividing circuit patterns into complementarypatterns complementary with each other and formed by openings and whichhas the complementary patterns arranged in the pattern forming regionsso that the pattern densities of the pattern forming regions becomesubstantially the same, to make a charged particle beam scan all of thepattern forming regions of the complementary mask and transfer thecomplementary patterns to an exposed body, and a shifting andtransferring step of shifting the mask by exactly one pattern formingregion worth of distance and making the charged particle beam scan allof the pattern forming regions of the complementary mask again totransfer the complementary patterns to the exposed body, and repeats theshifting and transferring step to transfer the complementary patterns ofall the pattern forming regions and thereby transfer the circuitpatterns to the exposed body.

[0024] To attain the above objects, a method of production of thesemiconductor device of the present invention has a step of using acomplementary mask, which is provided adjacent to each other with aplurality of pattern forming regions on which are arranged complementarypatterns obtained by dividing circuit patterns into complementarypatterns complementary with each other and formed by openings and whichhas the complementary patterns arranged in the pattern forming regionsso that the pattern densities of the pattern forming regions becomesubstantially the same, to make a charged particle beam scan all of thepattern forming regions of the complementary mask and transfer thecomplementary patterns to an exposed body, and a shifting andtransferring step of shifting the mask by exactly one pattern formingregion worth of distance and making the charged particle beam scan allof the pattern forming regions of the complementary mask again totransfer the complementary patterns to the exposed body, and repeats theshifting and transferring step to transfer the complementary patterns ofall the pattern forming regions and thereby transfer the circuitpatterns to the exposed body.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a schematic view of an example of a conventionalelectron beam exposure apparatus.

[0026]FIG. 2 is a plan view of patterns formed by transferring firstpatterns and second patterns to an exposure area by complementarystencil masks of a first embodiment.

[0027]FIG. 3 is a plan view of a first complementary stencil mask of thepresent embodiment.

[0028]FIG. 4 is a plan view of a second complementary stencil mask ofthe present embodiment.

[0029]FIG. 5 is a plan view enlarging first opening patterns of thefirst complementary stencil mask shown in FIG. 3.

[0030]FIG. 6 is a plan view enlarging second opening patterns of thesecond complementary stencil mask shown in FIG. 4.

[0031]FIG. 7 is a plan view of a state where gate layers and isolationlayers in composite patterns are divided into groups.

[0032]FIG. 8 is a plan view of the state where gate layers and isolationlayers in composite patterns are divided into groups.

[0033]FIGS. 9A and 9B are plan views of opening patterns forming pairsamong the first and second complementary stencil masks.

[0034]FIGS. 10A and 10B are plan views showing opening patterns formingpairs among the first and second complementary stencil masks.

[0035]FIG. 11 is a view schematically showing a flow of an exposureprocess at exposure and transfer to the exposure area.

[0036]FIG. 12 is a view schematically showing a flow of an exposureprocess at exposure and transfer to the exposure area.

[0037]FIG. 13 is a view schematically showing a flow of an exposureprocess at exposure and transfer to the exposure area.

[0038]FIG. 14 is a view schematically showing a flow of an exposureprocess at exposure and transfer to the exposure area.

[0039]FIG. 15 is a plan view of an actual transfer result correspondingto FIG. 11.

[0040]FIG. 16 is a plan view of an actual transfer result correspondingto FIG. 12.

[0041]FIG. 17 is a plan view of an actual transfer result correspondingto FIG. 13.

[0042]FIG. 18 is a plan view of an actual transfer result correspondingto FIG. 14.

[0043]FIG. 19 is a plan view of patterns formed by transferring the gatelayer patterns and the isolation layers to the exposure area by thecomplementary stencil masks of the second embodiment.

[0044]FIG. 20 is a plan view of a first complementary stencil mask of asecond embodiment.

[0045]FIG. 21 is a plan view of a second complementary stencil mask of asecond embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0046] Below, embodiments of the present invention will be explainedconcretely and in detail by giving embodiments and referring to theattached drawings. Note that the complementary masks etc. shown in thefollowing embodiments are illustrations for making facilitating theunderstanding of the present invention and that the present invention isnot limited to these illustrations.

[0047] First Embodiment

[0048] The present embodiment is an example of an embodiment ofcomplementary stencil masks. FIG. 2 is a plan view of patterns formed bytransferring first circuit patterns (gate layers) and second circuitpatterns (isolation layers) to an exposure area 50 by the complementarystencil masks of the present embodiment.

[0049]FIG. 3 is a plan view of a first complementary stencil mask havingfirst opening patterns for transferring first circuit patterns to theexposure area 50, while FIG. 4 is a plan view of a second complementarystencil mask having second opening patterns for transferring secondcircuit patterns to the exposure area 50.

[0050]FIG. 5 is a plan view enlarging the first opening patterns of thefirst complementary stencil mask shown in FIG. 3, while FIG. 6 is a planview enlarging the second opening patterns of the second complementarystencil mask shown in FIG. 4.

[0051] In the present embodiment, the first circuit patterns and thesecond circuit patterns configuring the semiconductor device are thegate layers and the isolation layers of memory circuits of SRAMs (staticrandom access memories).

[0052] Here, the first circuit patterns are gate layer patterns formedby exposure in the exposure layer, while the second circuit patterns areisolation layer patterns formed by exposure in an underlying layer.

[0053] In the present embodiment, first, the second complementarystencil mask 24 is used to form by exposure isolation layer patterns 38Aand 40A shown in FIG. 2 to form the underlying layer, then the firstcomplementary stencil mask 22 is used to form by exposure gate layerpatters 26A and 28A shown in FIG. 2 on this underlying layer.

[0054] The first complementary stencil mask 22 has two first patternforming regions 34 a and 34 b successively arranged adjacently eachother as shown in FIG. 3. The first pattern forming regions 34 a and 34b are provided with first opening patterns (complementary patterns) 26and 28 resembling the plurality of gate layer patterns 26A and 28A inthe exposure area 50.

[0055] In the first complementary stencil mask 22, all first openingpatterns 26 and 28 in the first pattern forming regions 34 a and 34 bare configured so as to resemble gate layer patterns 26A and 28A in theexposure area 50 shown in FIG. 2 in a one-to-one correspondence.Further, they are configured so that the group of the first openingpatterns 26 and 28 when overlaying all first pattern forming regions 34a and 34 b with each other resembles the group of all gate layerpatterns 26A and 28A in the exposure area 50.

[0056] The second complementary stencil mask 24 forms a pair with thefirst complementary stencil mask 22 and, as shown in FIG. 4, has twosecond pattern forming regions 46 a and 46 b successively arrangedadjacently each other and configured as pairs with the first patternforming regions 34 a and 34 b.

[0057] The second pattern forming regions 46 a and 46 b are providedwith second opening patterns (complementary patterns) 38 and 40resembling the plurality of isolation layer patterns 38A and 40A in theexposure area 50.

[0058] The second pattern forming regions 46 a and 46 b have secondopening patterns 38 and 40 resembling the isolation layer patterns 38Aand 40A below the gate layer functionally related to the gate layercorresponding to the first opening patterns 26 and 28 of the firstpattern forming regions 34 a and 34 b.

[0059] All second opening patterns 38 and 40 of the second patternforming regions 46 a and 46 b resemble to the isolation layer patterns38A and 40A of the isolation layer in the exposure area 50 shown in FIG.2 in a one-to-one correspondence.

[0060] Further, in all second opening patterns 38 and 40, the group ofthe second opening patterns 38 and 40 when overlaying all second patternforming regions 46 a and 46 b with each other resembles the group of allisolation layer patterns 38A and 40A in the exposure area 50.

[0061] The composite opening patterns comprised by the first openingpatterns 26 and 28 and the second opening patterns 38 and 40 whenoverlaying the first pattern forming regions 34 a and 34 b and thesecond pattern forming regions 46 a and 46 b with each other are givenpattern densities substantially the same for all of the pairs of thefirst pattern forming regions 34 a and 34 b and the second patternforming regions 46 a and 46 b.

[0062] The first and second complementary stencil masks 22. and 24 areconfigured so that the gate layer patterns 26A and 28A and the isolationlayer patterns 38A and 40A are exposed by projection onto the specimen21 shown in FIG. 1 by the charged particles passing through the firstopening patterns 26 and 28 and the second opening patterns 38 and 40 byfiring an electron beam.

[0063] In the complementary stencil masks of the present embodiment, anopening area density of the circuit patterns formed in the firstcomplementary stencil mask 22 can be greatly reduced and roughened,therefore the mechanical strengths of the first and second complementarystencil masks 22 and 24 can be improved.

[0064] For this reason, distortion or other deformation will not occurin the first and second complementary stencil masks 22 and 24, so thealignment between the specimen 21 and the complementary stencil masks 22and 24 can be performed accurately. Due to this, the circuit patternsare correctly exposed by projection on the specimen 21 and thus transferof accurate circuit patterns using two complementary stencil masks 22and 24 can be realized.

[0065] Note that the configuration relating to the first complementarystencil mask 22 explained in the present embodiment corresponds to anembodiment of the first aspect of the invention.

[0066] The “pattern density” referred to in the present descriptionmeans the degree of denseness of the patterns in the exposure area andmeans the ratio of the pattern area per unit area of the exposure area.The patterns existing in the exposure area are desirably divided so thatintervals between patterns become uniform so as to obtain a suitabledenseness state.

[0067] Details will be explained later, but the complementary stencilmasks of the present embodiment are used as follows. Namely, theexposure areas 50A and 50B of the exposed body shown in FIG. 11 areformed by exposure with the isolation layer patterns 38A and 40A by thesecond complementary stencil mask 24. Then, the process of forming byexposure the isolation layer patterns 38A and 40A in the exposure areas50A and 50B by the complementary stencil mask 24 is repeated again whileshifting the exposure areas 50A and 50B one by one to thereby form byexposure the isolation layer patterns 38A and 40A in the exposure areas50A and 50B.

[0068] Then, both of the exposure areas 50A and 50B to which theisolation layer patterns 38A and 40A are transferred are formed byexposure with the gate layer patterns 26A and 28A by the firstcomplementary stencil mask 22. Further, the process of forming byexposure the first pattern forming regions 34 a and 34 b in the exposureareas 50A and 50B by the first complementary stencil mask 22 is repeatedagain while shifting the exposure areas 50A and 50B one by one.

[0069] Next, an explanation will be given of the method of fabricationof the complementary stencil masks described above.

[0070] In the present method of fabrication, the first complementarystencil mask 22 comprised by the plurality of first pattern formingregions 34 a and 34 b successively arranged adjacently each other andhaving first opening patterns 26 and 28 resembling the plan shapes ofthe plurality of gate layers in the exposure area 50 shown in FIG. 2 isfabricated. Further, the second complementary stencil mask 24 forming apair with the complementary stencil mask 22 and comprised by secondpattern forming regions 46 a and 46 b having second opening patterns 38and 40 is fabricated.

[0071] Namely, in the present method of fabrication, first, as shown inFIG. 2, composite patterns 49 showing composite patterns comprised ofall gate layer patterns 26A and 28A of the exposure area 50 and allisolation layer patterns 38A and 40A of the exposure area 50 arefabricated.

[0072] Then, as shown in FIG. 7 and FIG. 8, the gate layers 26A and 28Aand the isolation layers 38A and 40A in the composite patterns 49 aredivided into groups so as to give pattern densities lower than thepattern density of the composite patterns 49 and substantially the sameas each other.

[0073] Then, two divided patterns 41 and 43 forming the compositepatterns comprised by the gate layer patterns 26A and 28A and theisolation layer patterns 38A and 40A for the groups are fabricated.

[0074] Next, as shown in FIG. 9A and FIG. 10A, first pattern formingregions 34 a and 34 b having first opening patterns 26 and 28corresponding to the gate layer patterns 26A and 28A constituting thedivided patterns 41 and 43 are fabricated.

[0075] Further, as shown in FIG. 9B and FIG. 10B, second pattern formingregions 46 a and 46 b having second opening patterns 38 and 40corresponding to the isolation layer patterns 38A and 40A and formingpairs with the first pattern forming regions 34 a and 34 b are prepared.The first pattern forming regions 34 a and 34 b and the second patternforming regions 46 a and 46 b are fabricated for every divided pattern.

[0076] Then, as shown in FIG. 3 and FIG. 5, the first complementarystencil mask 22 formed by successively arranging the first patternforming regions 34 a and 34 b adjacently each other is fabricated.Further, as shown in FIG. 4 and FIG. 6, the second complementary stencilmask 24 formed by successively arranging the second pattern formingregions 46 a and 46 b adjacently each other is fabricated.

[0077] By this series of steps, the complementary stencil masks 22 and24 of the present embodiment can be easily obtained.

[0078] In individual patterns of layers constituting MOS transistors orcapacitors forming a memory circuit, requirements for overlay accuracyof patterns compare severely with those between other patterns seenelectrically and in terms of device functions.

[0079] Accordingly, in the grouping of the complementary stencil masks22 and 24 of the present embodiment, the gate layers and the isolationlayers at parts related electrically and in terms of device functionswere assigned to the same groups as constituent members requiring strictoverlay accuracy with each other.

[0080] Also, paying attention to the gate layer, the division isdesirably carried out so that opening patterns do not become too closeto each other and so that pattern densities (area densities) of thedivided patterns 41 and 43 become equal as much as possible.

[0081] Next, an explanation will be given of an exposure method usingthe complementary stencil masks by referring to FIG. 11 to FIG. 14 andFIG. 15 to FIG. 18.

[0082]FIG. 11 to FIG. 14 are views schematically showing a flow of anexposure process at exposure and transfer to the exposure areas 50A and50B by step-wisely moving the specimen 21 of FIG. 1 by the operation ofa table in a state where the complementary stencil mask 22 or 24 is seton the mask stage. Illustration of the gate layer patterns and isolationlayer patterns to be transferred is omitted. FIG. 15 to FIG. 18 are planviews showing actual transfer results corresponding to FIG. 11 to FIG.14.

[0083] In the present exposure method, it is necessary to raise theoverlay accuracy between the stencil masks and the specimen, therefore,at the time of exposure by the electron beam exposure apparatus 10, theexposure work is proceeded with as shown in FIG. 15 to FIG. 18 whileperforming the alignment as follows.

[0084] Note that, in FIG. 11 to FIG. 14, a description is made bydeviating actually superimposed positions of the underlying layerpatterns and the complementary stencil mask for making the explanationeasy.

[0085] In the present exposure method, first, as shown in FIG. 11, theisolation layer patterns 38A and 40A are transferred to the exposureareas 50A and 50B arranged adjacently each other by the secondcomplementary stencil mask 24.

[0086] Then, the isolation layer patterns 38A and 40A are transferred tothe exposure areas 50A and 50B again by the second complementary stencilmask 24 while shifting the exposure areas 50A and 50B one by one by theoperation of the table (first shifting and transferring step).

[0087] Then, the first shifting and transferring step is repeated toform the exposure areas 50A and 50B arranged adjacently each other andto which the isolation layer patterns 38A and 40A are transferred.

[0088] Due to this, in the exposure areas 50A and 50B, the isolationlayer patterns 38A and 40A of the underlying layer shown in FIG. 15 areobtained. In FIG. 15, the isolation layer patterns 38A and 40A areformed by exposure in both of the exposure area 50A and the exposurearea 50B.

[0089] At the time of the above exposure, as shown in FIG. 11, alignmentmarks 30 and 31 are formed in the exposure area 50A and the exposurearea 50B.

[0090] Then, as shown in FIG. 12, at the exposure area 50A of theexposure areas 50A and 50B arranged adjacently each other and to whichthe isolation layer patterns 38A and 40A are transferred the gate layerpatterns 28A are transferred by the first pattern forming region 34 a ofthe first complementary stencil mask 22.

[0091] Due to this, the transfer patterns shown in FIG. 16 are obtained.

[0092] Further, the exposure areas 50A and 50B are shifted one by one bythe operation of the table, and the gate layer patterns 26A and 28A aretransferred to the exposure areas 50A and 50B again by the first patternforming regions 34 a and 34 b of the first complementary stencil mask 22(second shifting and transferring step). By this, the transfer patternsshown in FIG. 17 are obtained.

[0093] Thereafter, by repeating the second shifting and transferringstep, the transfer patterns shown in FIG. 18 are obtained.

[0094] In the above exposure method, the first pattern forming regions34 a and 34 b are provided with alignment marks 35 and 36 as shown inFIG. 12. The alignment marks 35 and 36 are aligned with the alignmentmarks 30 and 31 by using a program stored in the electron beam exposureapparatus 10 in advance.

[0095] In the case such as shown in FIG. 13, if making the alignmentmarks 36 of the first pattern forming region 34 b only alignment withthe alignment mark 31, the positioning time can be shortened. This isadvantageous in terms of the throughput.

[0096] In addition to this, if making the alignment marks 35 of thefirst pattern forming region 34 a also register with the alignment marks30 and 31, the throughput is slightly lowered, but the alignmentprecision is improved.

[0097] In the present embodiment, patterns of a certain semiconductordevice were divided into groups so as to make it easier to suppressmisalignment. Therefore, by properly alignment both complementarystencil masks 22 and 24 by the alignment marks at the time of exposure,it is possible to extremely accurately align elements not permittingmisalignment such as the gate layers and the isolation layersconstituting a MOS transistor.

[0098] In the present embodiment, in the exposure process, the alignmentinformation of the exposure areas of the underlying layer patterns canbe suitably weighted.

[0099] In this weighting, it is also possible to use the ratios of areasand quantities of the complementarily divided patterns of the underlyinglayer patterns comprised by the second opening patterns 38 and 40 or 78and 80 and the exposure layer patterns comprised by the first openingpatterns 26 and 28 or 66 and 68 transferred by exposure to theseunderlying layer patterns. Alternatively, it is also possible to utilizecharacteristics (quirks) inherent in an actually used mask writers (notillustrated) or electron beam exposure apparatuses 10.

[0100] According to such an exposure method, information of thecomplementary stencil masks when exposing the underlying layer patternscan be sufficiently used, so a higher overlay accuracy is obtained.

[0101] Also, alignment between the complementary stencil masks 24 and 64and the complementary stencil masks 22 and 62 when transferring byexposure circuit patterns divided among two or more complementarystencil masks is performed using the alignment marks for thecomplementary stencil masks 22 and 62 prepared in advance when exposingthe complementary stencil masks 24 and 64. Due to this, the overlayaccuracy between complementary stencil masks is greatly improved.

[0102] Note that the configuration in accordance with the exposuremethod using the first complementary stencil mask 22 explained in thepresent embodiment corresponds to an embodiment of the third aspect ofthe invention.

[0103] Second Embodiment

[0104]FIG. 19 is a plan view of patterns formed by transferring gatelayer patterns 66A and 68A and isolation layer patterns 78A and 80A toan exposure area 90 by the complementary stencil masks of the presentembodiment.

[0105]FIG. 20 is a plan view of the first complementary stencil maskhaving first opening patterns for transferring the gate layer patterns66A and 68A to the exposure area 90; and FIG. 21 is a plan view of asecond complementary stencil mask having second opening patterns fortransferring the isolation layer patterns 78A and 80A to the exposurearea 90.

[0106] As shown in FIG. 20, the complementary stencil mask 62 of thepresent embodiment has a plurality of first pattern forming regions 74 aand 74 b successively arranged adjacently each other. The first patternforming regions 74 a and 74 b have first opening patterns (complementarypatterns) 66 and 68 resembling the gate layer patterns 66A and 68A inthe exposure area 90.

[0107] In the first complementary stencil mask 62, all first openingpatterns 66 and 68 of the first pattern forming regions 74 a and 74 bresemble gate layer patterns 66A and 68A in the exposure area 90 in aone-to-one correspondence.

[0108] Further, in the first complementary stencil mask 62, the group ofthe first opening patterns 66 and 68 when overlaying all first patternforming regions 74 a and 74 b with each other is made to resemble thegroup of all gate layer patterns 66A and 68A in the exposure area 90.

[0109] As shown in FIG. 21, the second complementary stencil mask 64 isconfigured as a pair with the first pattern forming regions 74 a and 74b of the first complementary stencil mask 62. Also, the secondcomplementary stencil mask 64 has second pattern forming regions 86 aand 86 b successively arranged adjacently each other corresponding tothe first pattern forming regions 74 a and 74 b to be paired with andforms a pair with the first complementary stencil mask 62.

[0110] The second pattern forming regions 86 a and 86 b have secondopening patterns (complementary patterns) 78 and 80. The second openingpatterns 78 and 80 resemble the isolation layer patterns 78A and 80Ashown in FIG. 19 functionally related to the gate layers 66A and 68Acorresponding to the first opening patterns 66 and 68 of the firstpattern forming regions 74 a and 74 b and provided below the gatelayers.

[0111] In the second complementary stencil mask 64, all second openingpatterns 78 and 80 of the second pattern forming regions 86 a and 86 bresemble the isolation layer patterns 78A and 80A in the exposure area90 in a one-to-one correspondence.

[0112] Further, the group of the second opening patterns 78 and 80 whenoverlaying all second pattern forming regions 86 a and 86 b with eachother resembles the group of all isolation layer patterns 78A and 80A inthe exposure area 90.

[0113] In the complementary stencil masks 62 and 64, the compositeopening patterns comprised by the first and second opening patterns 66and 68 and 78 and 80 when overlaying the first and second patternforming regions 74 a and 74 b and 86 a and 86 b have pattern densitiessubstantially the same as each other for all pairs of first and secondpattern forming regions 74 a and 74 b and 86 a and 86 b.

[0114] Also the complementary stencil masks 62 and 64 of the presentembodiment can be fabricated in the same way as the method offabrication of the complementary stencil masks 22 and 24 of the firstembodiment.

[0115] Also, by using the completed complementary stencil masks 62 and64 in the same way as the complementary stencil masks 22 and 24 of thefirst embodiment, the circuit patterns can be accurately exposed byprojection onto the specimen 21.

[0116] In the complementary stencil masks of the present embodiment, theopening area density of the opening patterns formed in the firstcomplementary stencil mask 62 can be greatly reduced and the mechanicalstrengths of the first and second complementary stencil masks 62 and 64can be improved, so distortion or other deformation of the complementarystencil masks 62 and 64 will not occur.

[0117] For this reason, the alignment between the specimen 21 and thecomplementary stencil masks 62 and 64 can be accurately carried out, theopening patterns can be accurately exposed by projection, and accuratetransfer of circuit patterns using the two complementary stencil masks62 and 64 can be realized.

[0118] Further, in the first embodiment of the complementary stencilmasks, it was relatively easy to assign the complementary stencil masks22 and 24 for MOS transistors, capacitors, and other devices alltogether, but the present embodiment can be effectively applied to alogic circuit etc. not having repeating structures like a memorycircuit.

[0119] The present invention is not limited to the explanation of theabove embodiments. For example, in the present embodiments, theexplanation was given of the case where the first circuit patterns andsecond circuit patterns functionally related to the first circuitpatterns and provided in a layer different from the first circuitpatterns were the gate layers and the isolation layers of MOStransistors requiring strict overlay accuracy with each other, but theinvention is not limited to this. For example, they may also be acontact plug and the isolation layer connected to the contact plug.Also, they may be a metal interconnect layer and via plug connected tothe metal interconnect layer.

[0120] Industrual Applicability

[0121] The complementary masks of the present invention and the methodof fabrication of same, the exposure method, and the semiconductordevice and the production method of same can be utilized in the exposureprocess in the process of production of semiconductor devices.

LIST OF REFERENCES

[0122]10 . . . electron beam exposure apparatus

[0123]12 . . . electron beam source

[0124]14 . . . focusing optical system

[0125]16 . . . main deflector

[0126]18 . . . fine adjustment deflector

[0127]20 . . . stencil mask

[0128]21 . . . specimen

[0129]22 . . . first complementary stencil mask

[0130]26, 28 . . . first opening pattern

[0131]24 . . . second complementary stencil mask

[0132]26A, 28A . . . gate layer pattern

[0133]30, 31, 35, 36 . . . alignment mark

[0134]34 a, 34 b . . . first pattern forming region

[0135]38, 40 . . . second opening pattern

[0136]38A, 40A . . . isolation pattern

[0137]41, 43 . . . divided pattern

[0138]46 a, 46 b . . . second pattern forming region

[0139]49 . . . composite pattern

[0140]50, 50A, 50B . . . exposure area

[0141]62 . . . first complementary stencil mask

[0142]64 . . . second complementary stencil mask

[0143]66, 68 . . . first opening pattern

[0144]66A, 68A . . . gate layer pattern

[0145]78, 80 . . . second opening pattern

[0146]78A, 80A . . . isolation pattern

[0147]90 . . . exposure area

[0148] Eb . . . electron beam

1. A complementary mask which has a plurality of pattern forming regions(34 a, 34) having arranged on them complementary patterns (26, 28)obtained by dividing first circuit patterns into complementary patterns(26, 28) complementary with each other and formed by openings, and whichhave said complementary patterns (26, 28) arranged in the patternforming regions (34 a, 34 b) so that pattern densities of the patternforming regions (34 a, 34 b) become substantially the same.
 2. Acomplementary mask as set forth in claim 1, wherein said first circuitpatterns (26A, 28A) are patterns requiring strict overlay accuracy withrespect to second circuit patterns (38A, 40A) functionally related tosaid first circuit patterns (26A, 28A) and of a layer different fromsaid first circuit patterns (26A, 28A).
 3. A complementary mask as setforth in claim 2, wherein said first circuit patterns (26A, 28A) andsaid second circuit patterns (38A, 40A) are gate layers and isolationlayers of MOS transistors requiring strict overlay accuracy with eachother.
 4. A complementary mask as set forth in claim 2, wherein saidfirst circuit patterns (26A, 28A) and said second circuit patterns (38A,40A) are contact plugs of MOS transistors and isolation layers connectedto said contact plugs requiring strict overlay accuracy with each other.5. A complementary mask as set forth in claim 2, wherein said firstcircuit patterns (26A, 28A) and said second circuit patterns (38A, 40A)are metal interconnect layers of MOS transistors and via plugs connectedto the metal interconnect layers requiring strict overlay accuracy witheach other.
 6. An exposure method having: a step of using a firstcomplementary mask (22), which is provided adjacent to each other with aplurality of pattern forming regions (34 a, 34 b) on which are arrangedcomplementary patterns (26, 28) obtained by dividing first circuitpatterns (26A, 28A) into complementary patterns (26, 28) complementarywith each other and formed by openings, and which has said complementarypatterns (26, 28) arranged in the pattern forming regions (34 a, 34 b)so that the pattern densities of the pattern forming regions (34 a, 34b) become substantially the same, to make a charged particle beam scanall of the pattern forming regions (34 a, 34 b) of said firstcomplementary mask (22) and transfer the complementary patterns (26, 28)to an exposed body (21) and a shifting and transferring step of shiftingthe mask by exactly one said pattern forming region (34 a, 34 b) worthof distance and making the charged particle beam scan all of the patternforming regions (34 a, 34 b) of said first complementary mask (22) againto transfer the complementary patterns (26, 28) to said exposed body(21) and repeating said shifting and transferring step to transfer saidcomplementary patterns (26, 28) of all said pattern forming regions (34a, 34 b) and thereby transfer said first circuit patterns (26A, 28A) tosaid exposed body (21).
 7. An exposure method as set forth in claim 6,wherein said exposed body (21) is formed with second circuit patterns(38A, 40A) functionally related to said first circuit patterns (26A,28A) and requiring strict overlay accuracy, said method further has astep of transferring said second circuit patterns (38A, 40A) before thestep of transferring said first circuit patterns (26A, 28A), said stepof transferring said second circuit patterns (38A, 40A) having: a stepof using a second complementary mask which is provided adjacent to eachother with a plurality of pattern forming regions (46 a, 46 b) on whichare arranged complementary patterns (38, 40) obtained by dividing saidsecond circuit patterns (38A, 40A) into complementary patterns (38, 40)complementary with each other and formed by openings and which has saidcomplementary patterns (38, 40) arranged in the pattern forming regions(46 a, 46 b) so that the pattern densities of the pattern formingregions (46 a, 46 b) become substantially the same, to make a chargedparticle beam scan all of the pattern forming regions (46 a, 46 b) ofsaid second complementary mask (24) and transfer the complementarypatterns (38, 40) to an exposed body (21) and a shifting andtransferring step of shifting the mask by exactly one said patternforming region (46 a, 46 b) worth of distance and making the chargedparticle beam scan all of the pattern forming regions (46 a, 46 b) ofsaid second complementary mask (24) again to transfer the complementarypatterns (38, 40) to said exposed body (21) and repeating said shiftingand transferring step to transfer said complementary patterns (38, 40)of all said pattern forming regions (46 a, 46 b) and thereby transfersaid second circuit patterns (38A, 40A) to said exposed body (21).
 8. Amethod of fabrication of a complementary mask having: a step of dividingfirst circuit patterns (26A, 28A) into a plurality of pattern formingregions (34 a, 34 b) so that pattern densities become substantially thesame and assigning complementary patterns (26, 28) complementary witheach other to the pattern forming regions (34 a, 34 b) and a step offorming holes comprised by complementary patterns (26, 28) of thepattern forming regions (34 a, 34 b) so that the pattern forming regions(34 a, 34 b) are adjacent on the same mask substrate.
 9. A method offabrication of a complementary mask as set forth in claim 8, whereinsaid mask further has second circuit patterns (38A, 40A) functionallyrelated to said first circuit patterns (26A, 28A) and requiring strictoverlay accuracy, said step of assigning complementary patterns (26, 28)complementary with each other to the pattern forming regions (34 a, 34b) having: a step of fabricating composite patterns (39) comprised ofsaid first circuit patterns (26A, 28A) and second circuit patterns (38A,40A), a step of dividing said composite patterns (49) into a pluralityof divided patterns (41, 43) so that the pattern densities becomesubstantially the same, and a step of extracting complementary patterns(26, 28) corresponding to said first circuit patterns (26A, 28A)included in said divided patterns (41, 43) and assigning saidcomplementary patterns to said pattern forming regions (34 a, 34 b). 10.A semiconductor device obtained by a method having: a step of using acomplementary mask (22), which is provided adjacent to each other with aplurality of pattern forming regions (34 a, 34 b) on which are arrangedcomplementary patterns (26, 28) obtained by dividing circuit patterns(26A, 28A) into complementary patterns (26, 28) complementary with eachother and formed by openings and which has said complementary patterns(26, 28) arranged in the pattern forming regions (34 a, 34 b) so thatthe pattern densities of the pattern forming regions (34 a, 34 b) becomesubstantially the same, to make a charged particle beam scan all of thepattern forming regions (34 a, 34 b) of said complementary mask (22) andtransfer the complementary patterns (26, 28) to an exposed body (21) anda shifting and transferring step of shifting the mask by exactly onesaid pattern forming region (34 a, 34 b) worth of distance and makingthe charged particle beam scan all of the pattern forming regions (34 a,34 b) of said complementary mask (22) again to transfer thecomplementary patterns (26, 28) to said exposed body (21) and repeatingsaid shifting and transferring step to transfer said complementarypatterns (26, 28) of all said pattern forming regions (34 a, 34 b) andthereby transfer said circuit patterns (26A, 28A) to said exposed body(21).
 11. A method of production of a semiconductor device having: astep of using a complementary mask (22), which is provided adjacent toeach other with a plurality of pattern forming regions (34 a, 34 b) onwhich are arranged complementary patterns (26, 28) obtained by dividingcircuit patterns (26A, 28A) into complementary patterns (26, 28)complementary with each other and formed by openings and which has saidcomplementary patterns (26, 28) arranged in the pattern forming regions(34 a, 34 b) so that the pattern densities of the pattern formingregions (34 a, 34 b) become substantially the same, to make a chargedparticle beam scan all of the pattern forming regions (34 a, 34 b) ofsaid complementary mask (22) and transfer the complementary patterns(26, 28) to an exposed body (21) and a shifting and transferring step ofshifting the mask by exactly one said pattern forming region (34 a, 34b) worth of distance and making the charged particle beam scan all ofthe pattern forming regions (34 a, 34 b) of said complementary mask (22)again to transfer the complementary patterns (26, 28) to said exposedbody (21) and repeating said shifting and transferring step to transfersaid complementary patterns (26, 28) of all said pattern forming regions(34 a, 34 b) and thereby transfer said circuit patterns (26A, 28A) tosaid exposed body (21).